Constraint Intelligence for Digital Design
Ṛta brings order to timing intent, transforming constraints into trusted engineering knowledge through deterministic precision.
Ṛta deterministically validates your SDC before signoff tooling ever sees it: 119 documented rules, netlist-aware object resolution, constraint coverage, interactions, readiness and CI quality gates. Offline, reproducible, and honest about exactly what it checked.
The problem
Constraint files grow complex fast: generated clocks, cross-domain pairs, wildcard drift, duplicate exceptions, delays that silently exceed their clock period. By the time STA runs, small defects burn hours of signoff iteration.
Ṛta sits between constraint authoring and STA, catching structural and semantic problems with a deterministic engine, so the constraint set that reaches timing analysis is one you can defend in review.
SDC + optional structural Verilog netlist, multi-corner templates, TCL variables.
Rules, clock relations, design context, coverage, interactions, readiness: one deterministic pipeline.
Baselines, semantic diffs and quality gates: regressions fail the build, not the tapeout.
PrimeTime, Tempus and friends receive a constraint set that was checked before they saw it.
Features
Every feature produces evidence: rule codes, object resolution, coverage and provenance. Click any card for the full story, then jump straight into the tool.
119 documented rules with severity, evidence and source provenance on every finding.
→Primary, generated and virtual clocks with hierarchy, ancestry and relationship matrix.
→Structural Verilog context resolves ports, pins, cells and hierarchy, or honestly reports netlist-required.
→Object-level, bus-aware coverage evidence. Coverage ≠ correctness, and it always says so.
→Duplicates, overrides, contradictions and STA-review overlaps with dual-line provenance.
→Seven-dimension readiness review with blockers, review items and recommended actions.
→Snapshot baselines and semantic diff: NEW, RESOLVED, CHANGED, UNCHANGED.
→Deterministic gate policies with strict exit codes. Engine failures never pass.
→Bootstrap synthesis-ready SDC from CLI parameters: clocks, ports, constraints.
→Consistent formatting and sanity checks across every SDC in your flow.
→SDC ↔ JSON / YAML with lossless round-trip and diff-friendly output.
→Semantic constraint comparison: see what changed, not just which lines moved.
→Sweep directories of SDC files for check, lint and report in one command.
→PVT corner presets and multi-mode multi-corner constraint templates.
→Every SDC code documented: search, inspect, and cite in review.
→Reset trees, CDC, DFT scan, derate methodology: SDC-150 through 157.
→The platform
A fixed pipeline of parsers, checkers and analyzers. Same input, same output, every time: no model inference, no external API, no network dependency in the runtime.
# one command, from checkout or installed wheel
rta check design.sdc \
--netlist soc_top.v --top soc_top \
--baseline base.json --gate STRICT
# machine-readable everywhere
rta check design.sdc --json > result.json
rta report check design.sdc -o report.html
# exit codes: 0 pass · 1 findings · 2 invalid · 3 engine
echo $? # → 1 (findings found)
Trust boundary
SDC syntax and semantics, clock structure, semantic references, coverage, interactions, readiness and regression, within a documented support boundary.
Timing propagation, slack, delay calculation, .lib analysis, physical timing or signoff STA. Those remain with dedicated STA engines.
NETLIST_REQUIRED, TCL_EXECUTION_REQUIRED, UNSUPPORTED and NOT_VALIDATED constructs are surfaced, never silently assumed correct.
Listen
Hear what Ṛta does and why it matters — pick a language and press play.
English overview
Get started
Ṛta is on PyPI as rta-constraint-intelligence. One install, zero cloud dependency, works offline.
Ready when you are
Install from PyPI, drop in an SDC, and see findings with rule, severity, evidence and source line, or open the hosted workspace and try it in the browser.