Feature · Constraint Coverage
Ṛta shows which inputs, outputs, clocks and exceptions have constraints, down to individual bus bits. The unconstrained ones are the silent risks, and now they are visible.
In plain words
Coverage answers one question: "is this object mentioned in any constraint?" Every input port, output port, clock, and exception gets a state: covered, partial, or exempt. What has no constraint is a path with no timing requirement, which STA treats arbitrarily (usually too optimistically).
$ rta coverage top.sdc --netlist top.v --top top
Coverage:
inputs: 8 ports - 6 constrained, 2 partial
outputs: 4 ports - 3 constrained, 1 missing
clocks: 3 defined, 3 structurally resolved
▲ SDC-066 data_in[7:0] partially constrained
bits [7:4] have no set_input_delay
✗ SDC-064 output data_valid - no set_output_delay
Real-world example
An engineer constrains data_in[3:0] but the bus is 8 bits. The upper four bits have no input delay, so their paths have no timing requirement. STA quietly treats them as unconstrained; the violation appears only in signoff.
data_in[7:0]
bits [3:0] set_input_delay -clock clk_core
bits [7:4] NO CONSTRAINT - flagged
A path with no timing requirement gets whatever the tool decides. Coverage finds the gap first.
Per-bit granularity makes partial constraints visible instead of averaged away.
Coverage output feeds the readiness gate, so missing constraints fail the build.
Try it