Feature · Constraint Coverage

Know exactly what is constrained, and what is not

Ṛta shows which inputs, outputs, clocks and exceptions have constraints, down to individual bus bits. The unconstrained ones are the silent risks, and now they are visible.

In plain words

What does "coverage" mean?

Coverage answers one question: "is this object mentioned in any constraint?" Every input port, output port, clock, and exception gets a state: covered, partial, or exempt. What has no constraint is a path with no timing requirement, which STA treats arbitrarily (usually too optimistically).

  • Per-object, not a score. No single misleading percentage. Each input and output is listed with its state.
  • Bus-aware. A partially constrained data_in[7:0] is shown bit-by-bit, not hidden in an average.
  • Gap analysis. --missing-only lists exactly the unconstrained objects.
!Coverage is not correctness. A covered port can still have a wrong value. Ṛta says this every time.
$ rta coverage top.sdc --netlist top.v --top top Coverage: inputs: 8 ports - 6 constrained, 2 partial outputs: 4 ports - 3 constrained, 1 missing clocks: 3 defined, 3 structurally resolved ▲ SDC-066 data_in[7:0] partially constrained bits [7:4] have no set_input_delay ✗ SDC-064 output data_valid - no set_output_delay

Real-world example

The forgotten bus bits

An engineer constrains data_in[3:0] but the bus is 8 bits. The upper four bits have no input delay, so their paths have no timing requirement. STA quietly treats them as unconstrained; the violation appears only in signoff.

With Ṛta: coverage is computed per bit. The two missing bits are flagged immediately, with the exact bit range.
Same for clocks: a clock defined in SDC but with no structural fanout is reported as a dead clock that constrains nothing.
data_in[7:0] bits [3:0] set_input_delay -clock clk_core bits [7:4] NO CONSTRAINT - flagged

Unconstrained = arbitrary

A path with no timing requirement gets whatever the tool decides. Coverage finds the gap first.

Bus-aware detail

Per-bit granularity makes partial constraints visible instead of averaged away.

CI-friendly

Coverage output feeds the readiness gate, so missing constraints fail the build.

Try it

Measure your coverage

Coverage analysis
$ rta coverage your_block.sdc
$ rta coverage your_block.sdc --missing-only --netlist top.v --top top