Tool · Generator

Synthesis-ready SDC from one command

Instead of copy-pasting a template and hunting for the bits you changed, describe your design on the command line and let Ṛta write a complete, well-structured SDC file.

In plain words

What does the generator do?

You give it the essentials: design name, clocks, and options like uncertainty, operating condition, reset and scan. It produces a complete SDC with consistent section ordering and formatting, ready for review and validation.

The generated file follows the same conventions the linter enforces, so what you generate is what you'd lint, and what you'd check:

✓Repeatable: same flags, same file, every time.
✓Scan-ready: --scan --scan-port scan_en adds DFT-mode scaffolding.
✓Ideal or propagated: --propagated for post-CTS flows.


$ rta generate -d my_block -c clk=10.0:sys_clk \
    -c clk_io=5.0:clk_io --uncertainty 0.15 \
    --operating-condition SS_0P72V_16C \
    --ideal-reset --reset-port rst_n \
    --scan --scan-port scan_en -o my_block.sdc
✓ wrote my_block.sdc (synthesis-ready)

What you get

A file your team can review


# my_block - generated by Ṛta
set sdc_version 2.2
create_clock -name clk -period 10.0 [get_ports sys_clk]
create_clock -name clk_io -period 5.0 [get_ports clk_io]
set_clock_uncertainty 0.15 [get_clocks clk]
set_operating_conditions SS_0P72V_16C
set_ideal_network [get_ports rst_n]
set_case_analysis 0 [get_ports scan_en]

Kill copy-paste drift

Every new block starts from the same generator, not from someone's edited template.

Docs stay honest

Templates in your docs match what the generator produces, with no drift.

Validate in the same breath

Generate, then check: the two commands pair naturally.

Try it

Generate your first file

Generate an SDC

$ rta generate -d my_block -c clk=10.0:sys_clk --output my_block.sdc
$ rta check my_block.sdc # then validate it

Try it in the app ↗ All features