Feature · SDC Validation

Find constraint problems before STA does

Ṛta reads your SDC file and checks it against 119 documented rules. Every problem is reported with a rule code, severity, and the exact line, so you know what is wrong and how to fix it.

In plain words

What does "validating an SDC" mean?

An SDC file tells the timing tool how your design should be constrained. A small mistake can silently unconstrain a path. Validation is the automatic check that finds those mistakes while they are still cheap to fix.

Think of it like a spell-checker for timing constraints. You write the SDC, Ṛta reads it, and reports:

✓Errors: things that are definitely wrong (e.g. an input delay larger than the clock period).
✓Warnings: things that are probably wrong and need a look (e.g. a clock without a source).
✓Info: best-practice suggestions (e.g. add a propagated clock).


$ rta check top.sdc
✗ SDC-008  input delay 9.0ns ≥ clock period
           no timing margin - line 7
▲ SDC-030  missing input delay on data_in[7:0]
           line 9
◈ SDC-054  get_ports needs netlist context
           line 12

Real-world example

The typo that silently did nothing

An engineer types [get_ports datat_in] instead of data_in. The STA tool accepts it silently; the port doesn't exist, so the constraint applies to nothing, and the real port stays unconstrained. The problem is discovered weeks later in signoff.

✓With Ṛta: the typo is caught instantly. Every reference is checked against the netlist, and anything that cannot be verified is reported honestly instead of assumed.

✓Every finding carries evidence: rule, severity, affected object and source line, so review is fast and trustworthy.


$ rta check top.sdc --netlist top.v --top top
Design context: top (4 ports, 2 instances)
  ✓ references: 61/61 resolved
  ✗ SDC-055 [get_ports datat_in] - no such port
      closest match: data_in (L14)

Caught early, fixed cheap

A constraint bug found at validation costs minutes. The same bug found at signoff costs days of iteration.

Honest by design

If Ṛta cannot verify something, it says so. Nothing is silently assumed correct.

Same answer every time

Deterministic engine: no AI, no randomness. The same file gives the same findings on every machine.

Try it

Run it on your SDC

Validate a constraint file

$ rta check your_block.sdc
$ rta check your_block.sdc --netlist top.v --top top # design-aware
$ rta check your_block.sdc --json --output result.json # for CI

Try it in the app ↗ All features