Feature · Clock Intelligence

Understand your clocks before STA runs

Ṛta builds a complete map of every clock in your design, from primary to generated to virtual, and checks that the clock groups in your SDC match physical reality.

In plain words

What does "clock intelligence" mean?

Timing analysis works clock by clock. For STA to be correct, every clock must be defined, every generated clock must trace back to its master, and every pair of clocks must be declared in the right kind of clock group. Ṛta checks all of that automatically.

Clocks fall into three kinds, and Ṛta tracks all of them:

✓Primary clocks: the base clocks entering your block (e.g. from a PLL).
✓Generated clocks: clocks divided or multiplied from a master (e.g. a /2 divider).
✓Virtual clocks: reference clocks for I/O timing that do not exist in the design.

✓Every pair gets a verdict. Each clock pair is checked against its declared group: synchronous, asynchronous, or physically exclusive.


$ rta analyze clock-relations top.sdc
Clocks:       4 (2 primary, 2 generated)
Pairs:        6 · Sync: 3 · Async: 2 · Exclusive: 1

▲ SDC-060 clk_1x vs clk_2x - marked -asynchronous
  both primary on port clk_dual, 5.0 / 2.5 ns
  → use -physically_exclusive instead

Real-world example

The dual-clock port mistake

A port clk_dual can carry either a 5.0ns or a 2.5ns clock; only one is active at a time. The engineer declares them -asynchronous. That is wrong: asynchronous tells STA to analyze crosstalk and SI on paths that can never exist together. It should be -physically_exclusive.

✓With Ṛta: the mismatch is flagged with the exact reason and the fix, so the mistake never reaches signoff.

✓Completeness too: any clock pair not covered by a clock group is reported, never assumed fine.

Pair	Declared	Verdict
clk_core → clk_axi	-asynchronous	OK
clk_1x → clk_2x	-asynchronous	MISMATCH
clk_fast → div2	synchronous	OK
clk_scan → clk_core	ungrouped	MISSING

Wrong groups, wrong analysis

An incorrect clock group makes STA spend effort on impossible paths or skip real ones.

Generated clock math checked

Periods derived from -divide_by / -multiply_by / -edges are computed and sanity-checked.

Boundary is honest

Ṛta maps clock structure; it never claims to do timing propagation. That stays with STA.

Try it

Analyze your clocks

Clock relations analysis

$ rta analyze clock-relations your_block.sdc
$ rta analyze clock-relations your_block.sdc --netlist top.v --top top
$ rta report clock-relations your_block.sdc -o clocks.html

Try it in the app ↗ All features