RTL (Register Transfer Level) is the design abstraction where digital logic is described in HDL. It defines system behavior in terms of data flow between registers and operations.
🔗 Logic Synthesis
Synthesizes RTL into a gate-level netlist using standard cells. It applies optimization for area, power, and timing while preserving functionality.
Builds the VDD and VSS network using rings, straps, and rails. It ensures uniform power delivery and prepares the chip for EM/IR checks and tap cell insertion.
🧩 Placement
Places standard cells on legal sites while minimizing wirelength and satisfying timing. It’s the foundation for a congestion-free layout.
⏰ CTS
Clock Tree Synthesis ensures the clock signal reaches all sequential elements with balanced skew and minimal latency. Buffers and inverters are inserted strategically.
🛠 Routing
Establishes all physical connections between logic cells across multiple metal layers. Considers DRC rules, via counts, and path delays.
🚦 STA & Signoff
Static Timing Analysis checks setup/hold violations. Signoff includes LVS, DRC, IR drop, EM, and checks for tapeout readiness.