Pre-designed large block like SRAM or PLL, placed during floorplan.

Reusable design unit such as USB, PCIe, or processor core.

Basic gates (AND, OR, INV, FF) placed during PnR stage.

Connects substrate to ground to prevent latch-up issues.

Placed at ends of standard cell rows for structural closure.

Provides decoupling capacitance to stabilize local power grid.

Logic gates inserted for future engineering change orders (ECOs).

Used to tie signals safely to logic '1' or '0' level.

Fills gaps between standard cells to meet DRC and metal continuity.

Reserved region around macros or IOs to avoid overlaps or congestion.

Prevents cells from being placed in designated areas to reduce routing congestion.

Logical interface pins used for connecting signals into/out of the design.

Percentage of core area occupied by placed cells vs total available area.