Import LEF, tech LEF, Verilog netlist, SDC constraints, floorplan.tcl, and optionally DEF from synthesis.
Define the core size using die size and utilization. Place IO pads around the boundary as per pad ring definition.
Position logical input/output ports near their corresponding macros or logic groups to reduce wirelength and congestion.
Insert macros (SRAMs, PLLs, etc.) with pin orientation planning and keepout margins. Ensure symmetry and spacing.
Define spacing between macros and around corners. Use soft or physical-only blockages to reserve routing paths.
Set utilization (usually 60–80%) and create standard cell rows for placement inside the defined core area.
Add tap cells, end cap cells, filler cells, decap cells, and spare cells to meet DRC, latch-up, and ECO readiness.
Use region constraints, symmetry groups, placement blockages, and guide definitions for controlled placement.
Align IO pins with port locations. Use pin planning scripts or tools to optimize access, avoid corners, and reduce skew.
Run DRC, IR drop early checks, legality issues, congestion analysis, utilization reports, and tap cell spacing verification.
Save the milestone using DEF, Tcl snapshot, or database checkpoint to preserve reproducibility.